Daniele De Sensi
Assitant Professor, Sapienza University of Rome

I am an Associate Professor at Sapienza University of Rome. I was previously an Assistant Professor at Sapienza University of Rome, and a PostDoc researcher at ETH Zürich and University of Pisa. I received the Ph.D. in Computer Science from the University of Pisa.
My main reseach interests lie on the fields of Interconnection Networks, High Performance Computing, Green Computing, and Parallel Programming. You can find more about my research by checking the publications page.
If you have anything to discuss, feel free to send me an e-mail.
News
Oct 15, 2025 | 🎉 I’m happy to announce that two papers have been accepted at SC 2025 (Bine Trees: Enhancing Collective Operations by Optimizing Communication Locality and Uno: A One-Stop Solution for Inter- and Intra-Data Center Congestion Control and Reliable Connectivity) and one at EuroSys 2026 (REPS: Recycled Entropy Packet Spraying for Adaptive Load Balancing and Failure Mitigation). I am going to present the paper on Bine Trees in a few weeks at SC 2025. The paper introduces new algorithms for collective operations, reducing distance between communicating ranks and improving performance up to 80% on LUMI and MareNostrum5, 50% on Leonardo, and up to 5x on Fugaku. |
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Aug 27, 2024 | 🎉 I’m happy to announce that the paper Exploring GPU-to-GPU Communication: Insights into Supercomputer Interconnects have been accepted at SC ‘24. The paper focuses on GPU-GPU interconnect. We analyzed three top-10 supercomputers, on up to 4k NVIDIA and AMD GPUs, offering valuable insights to architects, researchers, practitioners, and developers. The paper is the outcome of a fruitful collaboration with NVIDIA, Cray HPE, ETH Zurich, CINECA, University of Trento, Vrije Universitiet, and University of Antwerp. You can find a preprint here. |
May 2, 2024 | 🎉 I’m happy to announce that the paper OSMOSIS: Enabling Multi-Tenancy in Datacenter SmartNICs have been accepted at USENIX ATC ‘24. OSMOSIS is a resource manager for SmartNICs to support multi-tenancy with low overhead. |
Apr 4, 2024 | 🎉 I’m happy to announce that a new paper have been accepted at HPDC ‘24. The paper introduces a performance model and new algorithms for reduce and allreduce on the Cerebras Wafer-Scale Engine (WSE), a novel architecture optimized for machine learning workloads. The new algorithms outperform the current vendor solutions by more than 3x. |
Feb 15, 2024 | 👨🏫 In partnership with the University of Trento and CINI, we will host in June a summer school focused on High-Performance Computing (HPC) (https://hpc-summer-school-24.disi.unitn.it/). I’ll be giving two lectures on interconnection networks and the process of writing HPC papers. If you’re interested, feel free to join. |