Daniele De Sensi

Assitant Professor, Sapienza University of Rome

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I am an Assistant Professor at Sapienza University of Rome. I was previously a PostDoc researcher at ETH Zürich and University of Pisa. I received the Ph.D. in Computer Science from the University of Pisa.

My main reseach interests lie on the fields of Interconnection Networks, High Performance Computing, Green Computing, and Parallel Programming. You can find more about my research by checking the publications page.

If you have anything to discuss, feel free to send me an e-mail.

News

Aug 27, 2024 🎉 I’m happy to announce that the paper Exploring GPU-to-GPU Communication: Insights into Supercomputer Interconnects have been accepted at SC ‘24. The paper focuses on GPU-GPU interconnect. We analyzed three top-10 supercomputers, on up to 4k NVIDIA and AMD GPUs, offering valuable insights to architects, researchers, practitioners, and developers. The paper is the outcome of a fruitful collaboration with NVIDIA, Cray HPE, ETH Zurich, CINECA, University of Trento, Vrije Universitiet, and University of Antwerp. You can find a preprint here.
May 2, 2024 🎉 I’m happy to announce that the paper OSMOSIS: Enabling Multi-Tenancy in Datacenter SmartNICs have been accepted at USENIX ATC ‘24. OSMOSIS is a resource manager for SmartNICs to support multi-tenancy with low overhead.
Apr 4, 2024 🎉 I’m happy to announce that a new paper have been accepted at HPDC ‘24. The paper introduces a performance model and new algorithms for reduce and allreduce on the Cerebras Wafer-Scale Engine (WSE), a novel architecture optimized for machine learning workloads. The new algorithms outperform the current vendor solutions by more than 3x.
Feb 15, 2024 👨‍🏫 In partnership with the University of Trento and CINI, we will host in June a summer school focused on High-Performance Computing (HPC) (https://hpc-summer-school-24.disi.unitn.it/). I’ll be giving two lectures on interconnection networks and the process of writing HPC papers. If you’re interested, feel free to join.
Dec 11, 2023 🎉 I’m happy to announce that two papers have been accepted at NSDI ‘24. The first one is about a new algorithm for allreduce on multidimensional torus networks that improves performance up to 3x compared to state-of-the-art algorithms (you can find a preprint here). The second one is on the design, implementation, and evaluation of the first-ever Slim Fly network deployment (here).

Selected Publications

2024

  1. Swing: Short-cutting Rings for Higher Bandwidth Allreduce
    Daniele De Sensi, Tommaso Bonato, David Saam, and 1 more author
    In 21th USENIX Symposium on Networked Systems Design and Implementation (NSDI 24), Apr 2024
  2. Canary: Congestion-aware in-network allreduce using dynamic trees
    Daniele De Sensi, Edgar Costa Molero, Salvatore Di Girolamo, and 2 more authors
    Future Generation Computer Systems, Apr 2024

2022

  1. Noise in the Clouds: Influence of Network Performance Variability on Application Scalability
    Daniele De Sensi, Tiziano De Matteis, Konstantin Taranov, and 3 more authors
    Proc. ACM Meas. Anal. Comput. Syst., Dec 2022
  2. HammingMesh: A Network Topology for Large-Scale Deep Learning
    Torsten Hoefler, Tommaso Bonato, Daniele De Sensi, and 7 more authors
    In Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis (SC’22), Nov 2022

2021

  1. Flare: Flexible in-Network Allreduce
    Daniele De Sensi, Salvatore Di Girolamo, Saleh Ashkboos, and 2 more authors
    In Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, Nov 2021

2020

  1. An In-Depth Analysis of the Slingshot Interconnect
    Daniele De Sensi, Salvatore Di Girolamo, Kim H. McMahon, and 2 more authors
    In Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, Nov 2020

2019

  1. Mitigating Network Noise on Dragonfly Networks Through Application-aware Routing
    Daniele De Sensi, Salvatore Di Girolamo, and Torsten Hoefler
    In Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, Nov 2019